Hi, all,
I am currently work with Leopardboard DM368.When I type the following command:
cat /proc/davinci_clocks ,
then , it shows arm_clk is 297MHz,
How can I make the Leopardboard DM368 at the 432MHz? and how to do that ?
thanks
Hi,
You would need to recompile and install the UBL on the board. If you're using DVSDK 4.02 that file should be located on:
ti-dvsdk_dm365-evm_4_02_00_06/psp/flash-utils/DM36x/Common/src/device.c
there you will find definitions for the PLL dividers/multipliers and some code that writes the appropriate registers.
It would be an easy task only if you're familiar with the DM365 clocking architecture (sprufg5a.pdf) and if you know how to recompile/install the UBL.
Regards,
Pablo BarrantesEmbedded Software EngineerRidgeRun
Firstly, sorry to others on this forum for not providing some code that I promised - I have several other work issues to take care of first. Also there are copyright issues. But I hope I can provide some material soon.
We received our sample Leopardboard DM368 units (LI-TB02) recently. Very fast delivery! But they just work the same as the DM365 Leopardboard of course, without a bootloader modification. The booloader is responsible for setting up the PLL frequencies, which are picked up by the kernel at boot time and you can inspect them with 'cat /proc/davinci_clocks'.
Using the RidgeRun DM365 free SDK, to get the DM368 to run at full speed you need to modify the SDK file bsp/arch-dm365/u-boot/ti-flash-utils-1.5/src/device.c. Then do 'make bootloader' and 'make installbootloader', 'make install' to update it.
We used the TI DVSDK4.02 for DM368 as a guide, this also has a device.c but it's unsuitable for the Leopardboard due to different clock layout etc. So we took the RidgeRun device.c and modified the DEVICE_PLL1Init(), DEVICE_PLL2Init(),and DEVICE_DDR2Init() functions to setup for DM368.
Changes to DEVICE_PLL1Init() and DEVICE_PLL2Init() are just PLL multiplier and divider settings to get the higher frequency for the ARM and other DM368 devices. Some devices like video encoder need to be kept running at the same frequency e.g. 27MHz for VICP and 74.25MHz for HDVICP. VICP is very sensitive to frequency error e.g. less than 0.1% can introduce significant color distortions. For that reason we ended up overclocking the core by about 3% in order to get accurate divider ratios. So our CPU runs at 445.5MHz not 432MHz, at least for now (not likely to cause any problem, we could underclock instead of overclock and get accurate ratios as well). That allows the HDVICP to run at 74.24MHz, which is close enough to the rated 74.25MHz. Also the PLL that drives the internal DM368 engines is made about 3% higher, 702MHz instead of 680MHz. This allows the VICP clock of precisely 27.00MHz to be generated.
The DEVICE_DDR2Init() was just taken straight from the TI code, as well as the constants this function uses. Also we define the DDR_FREQ as well as #define the function DDR_Get_Val(), since the coded version seemed not to link due to some math library missing. It works out the correct DDR waitstates based on the desired DDR clock which is now 340MHz.
We found the performance is as good as hoped, CPU is 222 BogoMIPS and video encoding etc. seems to run about 50% faster. So, well worth it and we will definitely be using the Leopardboard DM368 in future projects. No problems noted with video output in SD or HD modes. However, we have not fully tested all the Leopardboard features, so it's possible that some of the other features do not work properly. If we find a problem, it can certainly be fixed up by tweaking the PLL ratios again.
Below I pasted the modified device.c code. I have #define'd IS_DM368 as a switch.
Enjoy!
Mark Lesha, ANSTO
--------------------------------- 8< snip 8< ----------------------------------------------
/* -------------------------------------------------------------------------- FILE : device.c PROJECT : TI Booting and Flashing Utilities AUTHOR : Sandeep Paulraj DESC : This file provides low-level, device-specific init functions for use the DM36x device.-------------------------------------------------------------------------- */ // General type include#include "tistdtypes.h"// This module's header file#include "device.h"// Debug module#include "debug.h"// Utility functions#include "util.h"/************************************************************* Explicit External Declarations *************************************************************/extern __FAR__ VUint32* DDRStart;/************************************************************* Local Macro Declarations *************************************************************//************************************************************* Local Typedef Declarations *************************************************************//************************************************************* Local Function Declarations *************************************************************//************************************************************* Local Variable Definitions *\***********************************************************/ static const Uint32 PLL1_Mult = DEVICE_PLL1_MULTIPLIER; static const Uint32 PLL2_Mult = DEVICE_PLL2_MULTIPLIER; /************************************************************* Global Variable Definitions *************************************************************/const String devString = "DM36x";#define GPINT_GPEN (unsigned int *)(0x01C21C08) // WDT special function#define GPTDAT_GPDIR (unsigned int *)(0x01C21C0c) // WDT special function/************************************************************* Global Function Definitions *************************************************************/Uint32 DEVICE_init(){ Uint32 status = E_PASS; Uint32 temp; // Mask all interrupts AINTC->INTCTL = 0x4; AINTC->EABASE = 0x0; AINTC->EINT0 = 0x0; AINTC->EINT1 = 0x0; // Clear all interrupts AINTC->FIQ0 = 0xFFFFFFFF; AINTC->FIQ1 = 0xFFFFFFFF; AINTC->IRQ0 = 0xFFFFFFFF; AINTC->IRQ1 = 0xFFFFFFFF;#ifndef SKIP_LOW_LEVEL_INIT POR_RESET(); // System PSC setup - enable all DEVICE_PSCInit(); DEVICE_pinmuxControl(0,0xFFFFFFFF,0x00FD0000); // All Video Inputs DEVICE_pinmuxControl(1,0xFFFFFFFF,0x00145555); // All Video Outputs DEVICE_pinmuxControl(2,0xFFFFFFFF,0x000000DA); // EMIFA DEVICE_pinmuxControl(3,0xFFFFFFFF,0x00180000); // SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs DEVICE_pinmuxControl(4,0xFFFFFFFF,0x55555555); // MMC/SD0 instead of MS, SPI0 GPIO->DIR02 &= 0xfeffffff; GPIO->CLRDATA02 = 0x01000000; //PLL1 Setup#if defined(ARM297_DDR270_OSC24) if (status == E_PASS) status |= DEVICE_PLL1Init_270MHZ(PLL1_Mult);#elif defined(ARM270_DDR216_OSC24) if (status == E_PASS) status |= DEVICE_PLL1Init_216MHZ(PLL1_Mult);#elif defined(ARM297_DDR277_OSC27) if (status == E_PASS) status |= DEVICE_PLL1Init_297MHZ_OSC27MHZ(PLL1_Mult);#elif defined(ARM216_DDR173_OSC19P2) if (status == E_PASS) status |= DEVICE_PLL1Init_216MHZ_OSC19P2MHZ(PLL1_Mult);#else if (status == E_PASS) status |= DEVICE_PLL1Init(PLL1_Mult);#endif // PLL2 setup#if defined(ARM270_DDR216_OSC24) if (status == E_PASS) status |= DEVICE_PLL2Init_270MHZ();#elif defined(ARM297_DDR277_OSC27) if (status == E_PASS) status |= DEVICE_PLL2Init_277MHZ();#elif defined(ARM216_DDR173_OSC19P2) if (status == E_PASS) status |= DEVICE_PLL2Init_173MHZ(); #else if (status == E_PASS) status |= DEVICE_PLL2Init();#endif // DDR2 setup#if defined(ARM297_DDR270_OSC24) if (status == E_PASS) status |= DEVICE_DDR2Init_270MHZ();#elif defined(ARM270_DDR216_OSC24) if (status == E_PASS) status |= DEVICE_DDR2Init_216MHZ();#elif defined(ARM297_DDR277_OSC27) if (status == E_PASS) status |= DEVICE_DDR2Init_277MHZ();#elif defined(ARM216_DDR173_OSC19P2) if (status == E_PASS) status |= DEVICE_DDR2Init_173MHZ(); #else if (status == E_PASS) status |= DEVICE_DDR2Init();#endif#endif // AEMIF Setup if (status == E_PASS) status |= DEVICE_EMIFInit(); temp = AEMIF->NANDERRADD1; // UART0 Setup if (status == E_PASS) status |= DEVICE_UART0Init(); // TIMER0 Setup if (status == E_PASS) status |= DEVICE_TIMER0Init(); // I2C0 Setup if (status == E_PASS) status |= DEVICE_I2C0Init(); return status;}void POR_RESET(){ if ((PLL1->RSTYPE)&3) { VPSS_SYNC_RESET(); // VPSS sync reset *GPINT_GPEN = 0x00020000; *GPTDAT_GPDIR = 0x00020002; while(1); }}void VPSS_SYNC_RESET(){ unsigned int PdNum = 0; SYSTEM->VPSS_CLKCTL |= 0x00000080; // VPSS_CLKMD 1:1 //LPSC SyncReset DDR Clock Enable PSC->MDCTL[47] = ((PSC->MDCTL[47] & 0xffffffe0) | 0x00000001); PSC->PTCMD = (1<<PdNum); while(! (((PSC->PTSTAT >> PdNum) & 0x00000001) == 0)); while(!((PSC->MDSTAT[47] & 0x0000001F) == 0x1)); }void DEVICE_LPSCTransition(Uint8 module, Uint8 domain, Uint8 state){ // Wait for any outstanding transition to complete while ( (PSC->PTSTAT) & (0x00000001 << domain) ); // If we are already in that state, just return if (((PSC->MDSTAT[module]) & 0x1F) == state) return; // Perform transition PSC->MDCTL[module] = ((PSC->MDCTL[module]) & (0xFFFFFFE0)) | (state); PSC->PTCMD |= (0x00000001 << domain); // Wait for transition to complete while ( (PSC->PTSTAT) & (0x00000001 << domain) ); // Wait and verify the state while (((PSC->MDSTAT[module]) & 0x1F) != state); }void DEVICE_pinmuxControl(Uint32 regOffset, Uint32 mask, Uint32 value){ SYSTEM->PINMUX[regOffset] &= ~mask; SYSTEM->PINMUX[regOffset] |= (mask & value);}DEVICE_BootMode DEVICE_bootMode( void ){ return (DEVICE_BootMode) ((SYSTEM->BOOTCFG & DEVICE_BOOTCFG_BOOTMODE_MASK) >> DEVICE_BOOTCFG_BOOTMODE_SHIFT);}DEVICE_BusWidth DEVICE_emifBusWidth( void ){ if ( ( (SYSTEM->BOOTCFG & DEVICE_BOOTCFG_EMIFWIDTH_MASK) >> DEVICE_BOOTCFG_EMIFWIDTH_SHIFT) & 0x1 ) { return DEVICE_BUSWIDTH_16BIT; } else { return DEVICE_BUSWIDTH_8BIT; }}void DEVICE_PSCInit(){ unsigned char i=0; unsigned char lpsc_start; unsigned char lpsc_end,lpscgroup,lpscmin,lpscmax; unsigned int PdNum = 0; lpscmin =0; lpscmax =2; for(lpscgroup=lpscmin ; lpscgroup <=lpscmax; lpscgroup++) { if(lpscgroup==0) { lpsc_start = 0; // Enabling LPSC 3 to 28 SCR first lpsc_end = 28; } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */ lpsc_start = 38; lpsc_end = 47; } else { lpsc_start = 50; lpsc_end = 51; } //NEXT=0x3, Enable LPSC's for(i=lpsc_start; i<=lpsc_end; i++) { // CSL_FINS(CSL_PSC_0_REGS->MDCTL[i], PSC_MDCTL_NEXT, 0x3); PSC->MDCTL[i] |= 0x3; } //Program goctl to start transition sequence for LPSCs //CSL_PSC_0_REGS->PTCMD = (1<<PdNum); /*Kick off Power Domain 0 Modules*/ PSC->PTCMD = (1<<PdNum); //Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0 //while(! (((CSL_PSC_0_REGS->PTSTAT >> PdNum) & 0x00000001) == 0)); while(! (((PSC->PTSTAT >> PdNum) & 0x00000001) == 0)); //Wait for MODSTAT = ENABLE from LPSC's for(i=lpsc_start; i<=lpsc_end; i++) { // while(!((CSL_PSC_0_REGS->MDSTAT[i] & 0x0000001F) == 0x3)); while(!((PSC->MDSTAT[i] & 0x0000001F) == 0x3)); } } }// MJL set DM365/DM368 mode operation here...#define IS_DM368 1 // 0 for DM365 (297MHz), 1 for DM368 (432MHz)//Uint32 DEVICE_PLL1Init(Uint32 PLLMult){ unsigned int CLKSRC=0x0; unsigned int j; /*Power up the PLL*/ PLL1->PLLCTL &= 0xFFFFFFFD; PLL1->PLLCTL &= 0xFFFFFEFF; PLL1->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL1->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL1->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(150); // PLLRST=1(reset assert) PLL1->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL1->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL1 // MJL tweak the 680MHz clock up slightly to 702MHz to get a more accurate SD VENC clock (overclocked +3.2%) PLL1->PLLM = (IS_DM368?/*0x55*/117:0x51); // VCO will 24*2M/N+1 = 486Mhz (DM365F) / 680MHz (DM368) PLL1->PREDIV = 0x8000|(IS_DM368?/*0x5*/7:0x7); PLL1->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 //Program the PostDiv for PLL1 PLL1->POSTDIV = 0x8000; // same for DM365/DM368 // Post divider setting for PLL1 // MJL did not change these dividers because apparently they are able to be increased in proportion with the CPU clock PLL1->PLLDIV2 = 0x8001; // same for DM365/DM368 PLL1->PLLDIV3 = 0x8001; // same for DM365/DM368 // POST DIV 486/2 -> MJCP/HDVICP PLL1->PLLDIV4 = 0x8003; // same for DM365/DM368 // POST DIV 486/4 -> EDMA/EDMA CFG PLL1->PLLDIV5 = 0x8001; // same for DM365/DM368 // POST DIV 486/2 -> VPSS // PLL1->PLLDIV6 = 0x8000|(IS_DM368?25:0x11); // 27Mhz POST DIV 486/18, or 702/26 -> VENC PLL1->PLLDIV7 = 0x8000; // POST DIV 486/2 -> DDR PLL1->PLLDIV8 = 0x8000|(IS_DM368?0x6:0x3); // POST DIV 486/4 -> MMC0/SD0 PLL1->PLLDIV9 = 0x8001; // POST DIV 486/2 -> CLKOUT UTIL_waitLoop(300); /*Set the GOSET bit */ PLL1->PLLCMD = 0x00000001; // Go UTIL_waitLoop(300); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL0_CONFIG) & 0x07000000) == 0x07000000)); /*Enable the PLL Bit of PLLCTL*/ PLL1->PLLCTL |= 0x00000001; // PLLEN=0 return E_PASS;}Uint32 DEVICE_PLL1Init_270MHZ(Uint32 PLLMult){ unsigned int CLKSRC=0x0; unsigned int j; /*Power up the PLL*/ PLL1->PLLCTL &= 0xFFFFFFFD; PLL1->PLLCTL &= 0xFFFFFEFF; PLL1->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL1->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL1->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(150); // PLLRST=1(reset assert) PLL1->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL1->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL1 PLL1->PLLM = 0x2D; // VCO will 24*2M/N+1 = 540 Mhz PLL1->PREDIV = 0x8000|0x3; PLL1->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 //Program the PostDiv for PLL1 PLL1->POSTDIV = 0x8000; // Post divider setting for PLL1 PLL1->PLLDIV2 = 0x8001; PLL1->PLLDIV3 = 0x8001; // POST DIV 540/2 -> MJCP/HDVICP PLL1->PLLDIV4 = 0x8003; // POST DIV 540/4 -> EDMA/EDMA CFG PLL1->PLLDIV5 = 0x8001; // POST DIV 540/2 -> VPSS PLL1->PLLDIV6 = 0x8013; // 27Mhz POST DIV 540/20 -> VENC PLL1->PLLDIV7 = 0x8000; // POST DIV 540/2 -> DDR PLL1->PLLDIV8 = 0x8003; // POST DIV 540/4 -> MMC0/SD0 PLL1->PLLDIV9 = 0x8001; // POST DIV 540/2 -> CLKOUT UTIL_waitLoop(300); /*Set the GOSET bit */ PLL1->PLLCMD = 0x00000001; // Go UTIL_waitLoop(300); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL0_CONFIG) & 0x07000000) == 0x07000000)); /*Enable the PLL Bit of PLLCTL*/ PLL1->PLLCTL |= 0x00000001; // PLLEN=0 return E_PASS;}Uint32 DEVICE_PLL1Init_216MHZ(Uint32 PLLMult){ unsigned int CLKSRC=0x0; unsigned int j; /*Power up the PLL*/ PLL1->PLLCTL &= 0xFFFFFFFD; PLL1->PLLCTL &= 0xFFFFFEFF; PLL1->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL1->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL1->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(150); // PLLRST=1(reset assert) PLL1->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL1->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL1 PLL1->PLLM = 0x9; // VCO will 24*2M/N+1 = 432 Mhz PLL1->PREDIV = 0x8000|0x0; PLL1->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 //Program the PostDiv for PLL1 PLL1->POSTDIV = 0x8000; // Post divider setting for PLL1 PLL1->PLLDIV2 = 0x8001; PLL1->PLLDIV3 = 0x8001; // POST DIV 432/2 -> MJCP/HDVICP PLL1->PLLDIV4 = 0x8003; // POST DIV 432/4 -> EDMA/EDMA CFG PLL1->PLLDIV5 = 0x8001; // POST DIV 432/2 -> VPSS PLL1->PLLDIV7 = 0x8000; // POST DIV 432/2 -> DDR PLL1->PLLDIV8 = 0x8003; // POST DIV 432/4 -> MMC0/SD0 PLL1->PLLDIV9 = 0x8001; // POST DIV 432/2 -> CLKOUT UTIL_waitLoop(300); /*Set the GOSET bit */ PLL1->PLLCMD = 0x00000001; // Go UTIL_waitLoop(300); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL0_CONFIG) & 0x07000000) == 0x07000000)); /*Enable the PLL Bit of PLLCTL*/ PLL1->PLLCTL |= 0x00000001; // PLLEN=0 return E_PASS;}Uint32 DEVICE_PLL1Init_297MHZ_OSC27MHZ(Uint32 PLLMult){ unsigned int CLKSRC=0x0; unsigned int j; /*Power up the PLL*/ PLL1->PLLCTL &= 0xFFFFFFFD; PLL1->PLLCTL &= 0xFFFFFEFF; PLL1->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL1->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL1->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(150); // PLLRST=1(reset assert) PLL1->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL1->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL1 PLL1->PLLM = 0x2c; // VCO will 24*2M/N+1 = 594 Mhz PLL1->PREDIV = 0x8000|0x3; PLL1->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 //Program the PostDiv for PLL1 PLL1->POSTDIV = 0x8000; // Post divider setting for PLL1 PLL1->PLLDIV2 = 0x8001; PLL1->PLLDIV3 = 0x8001; // POST DIV 594/2 -> MJCP/HDVICP PLL1->PLLDIV4 = 0x8003; // POST DIV 594/4 -> EDMA/EDMA CFG PLL1->PLLDIV5 = 0x8003; // POST DIV 594/4 -> VPSS PLL1->PLLDIV6 = 0x8015; // POST DIV 594/22 - 27 MHZ ->VENC SD PLL1->PLLDIV7 = 0x8000; PLL1->PLLDIV8 = 0x8003; // POST DIV 594/4 -> MMC0/SD0 PLL1->PLLDIV9 = 0x8001; // POST DIV 594/2 -> CLKOUT UTIL_waitLoop(300); /*Set the GOSET bit */ PLL1->PLLCMD = 0x00000001; // Go UTIL_waitLoop(300); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL0_CONFIG) & 0x07000000) == 0x07000000)); /*Enable the PLL Bit of PLLCTL*/ PLL1->PLLCTL |= 0x00000001; // PLLEN=0 return E_PASS;}Uint32 DEVICE_PLL1Init_216MHZ_OSC19P2MHZ(Uint32 PLLMult){ unsigned int CLKSRC=0x0; unsigned int j; /*Power up the PLL*/ PLL1->PLLCTL &= 0xFFFFFFFD; PLL1->PLLCTL &= 0xFFFFFEFF; PLL1->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL1->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL1->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(150); // PLLRST=1(reset assert) PLL1->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL1->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL1 PLL1->PLLM = 0x2d; // VCO will 24*2M/N+1 = 432 Mhz PLL1->PREDIV = 0x8000|0x3; PLL1->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 // for(j=0; j<0x100; j++) {} PLL1->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 //Program the PostDiv for PLL1 PLL1->POSTDIV = 0x8000; // Post divider setting for PLL1 PLL1->PLLDIV2 = 0x8001; PLL1->PLLDIV3 = 0x8001; // POST DIV 432/2 -> MJCP/HDVICP PLL1->PLLDIV4 = 0x8003; // POST DIV 432/4 -> EDMA/EDMA CFG PLL1->PLLDIV5 = 0x8003; // POST DIV 432/4 -> VPSS PLL1->PLLDIV6 = 0x800f; // POST DIV 432/16 - 27 MHZ ->VENC SD PLL1->PLLDIV7 = 0x8000; PLL1->PLLDIV8 = 0x8003; // POST DIV 432/4 -> MMC0/SD0 PLL1->PLLDIV9 = 0x8001; // POST DIV 432/2 -> CLKOUT UTIL_waitLoop(300); /*Set the GOSET bit */ PLL1->PLLCMD = 0x00000001; // Go UTIL_waitLoop(300); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL0_CONFIG) & 0x07000000) == 0x07000000)); /*Enable the PLL Bit of PLLCTL*/ PLL1->PLLCTL |= 0x00000001; // PLLEN=0 return E_PASS;}Uint32 DEVICE_PLL2Init(){ unsigned int CLKSRC=0x0; /*Power up the PLL*/ PLL2->PLLCTL &= 0xFFFFFFFD; /*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/ /*VDB has input on MXI pin */ PLL2->PLLCTL &= 0xFFFFFEFF; PLL2->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL2->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL2->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(50); // PLLRST=1(reset assert) PLL2->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL2->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL2 // MJL in order to get precise 74.25MHz video clock, up-adjusted the frequency slightly to 445.5MHz (+3.125% overclocked CPU) // Note M is 10 bits and PREDIV 5 bits. // Close ratios: 24*(2*232)/(24+1)=445.44 (-0.013%), 24*(2*65)/(6+1)=445.71 (+0.048%) PLL2->PLLM = (IS_DM368?/*0x09*/232:0x63); // VCO will 24*2M/N+1 = 594Mhz (DM365) / 432MHz (DM368) PLL2->PREDIV = 0x8000|(IS_DM368?/*0x0*/24:0x7); PLL2->POSTDIV = 0x8000; PLL2->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 PLL2->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 PLL2->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 PLL2->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 // Post divider setting for PLL2 PLL2->PLLDIV2 = 0x8000|(IS_DM368?0x00:0x01); // 594/2 =297 Mhz (DM365), 432MHz (DM368) -> ARM PLL2->PLLDIV4 = 0x8000|(IS_DM368?0x15:0x1C); // POST DIV 594/29 = 20.48 (DM365), 20.24 (DM368) -> VOICE PLL2->PLLDIV5 = 0x8000|(IS_DM368?0x05:0x07); // POST DIV 594/8 = 74.25 (DM365), 74.24 (DM368) -> VIDEO HD //GoCmd for PostDivider to take effect PLL2->PLLCMD = 0x00000001; UTIL_waitLoop(150); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL1_CONFIG) & 0x07000000) == 0x07000000)); UTIL_waitLoop(4100); //Enable the PLL2 PLL2->PLLCTL |= 0x00000001; // PLLEN=0 //do this after PLL's have been set up SYSTEM->PERI_CLKCTRL = (IS_DM368?0x243F04FC:0x243F04FC); return E_PASS; }Uint32 DEVICE_PLL2Init_270MHZ(){ unsigned int CLKSRC=0x0; /*Power up the PLL*/ PLL2->PLLCTL &= 0xFFFFFFFD; /*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/ /*VDB has input on MXI pin */ PLL2->PLLCTL &= 0xFFFFFEFF; PLL2->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL2->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL2->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(50); // PLLRST=1(reset assert) PLL2->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL2->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL2 PLL2->PLLM = 0x2D; // VCO will 24*2M/N+1 = 540Mhz PLL2->PREDIV = 0x8000|0x7; PLL2->POSTDIV = 0x8000; PLL2->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 PLL2->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 PLL2->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 PLL2->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 // Post divider setting for PLL2 PLL2->PLLDIV2 = 0x8000; // 270/1 =270 Mhz -> ARM PLL2->PLLDIV4 = 0x8005; // POST DIV 270/6 VOICE PLL2->PLLDIV5 = 0x8009; // POST DIV 270/10 = 27MHZ ->VIDEO SD //GoCmd for PostDivider to take effect PLL2->PLLCMD = 0x00000001; UTIL_waitLoop(150); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL1_CONFIG) & 0x07000000) == 0x07000000)); UTIL_waitLoop(4100); //Enable the PLL2 PLL2->PLLCTL |= 0x00000001; // PLLEN=0 //do this after PLL's have been set up SYSTEM->PERI_CLKCTRL = 0x243F04FC; return E_PASS; }Uint32 DEVICE_PLL2Init_277MHZ(){ unsigned int CLKSRC=0x0; /*Power up the PLL*/ PLL2->PLLCTL &= 0xFFFFFFFD; /*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/ /*VDB has input on MXI pin */ PLL2->PLLCTL &= 0xFFFFFEFF; PLL2->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL2->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL2->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(50); // PLLRST=1(reset assert) PLL2->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL2->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL2 PLL2->PLLM = 0x100; // VCO will 24*2M/N+1 = 552.96Mhz PLL2->PREDIV = 0x8000|0x18; PLL2->POSTDIV = 0x8000; PLL2->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 PLL2->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 PLL2->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 PLL2->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 // Post divider setting for PLL2 PLL2->PLLDIV2 = 0x8000; // POST DIV 552.96/1=552.96mhz -> ARM926/HDVICPCont PLL2->PLLDIV3 = 0x8001; // POST DIV 552.96/2=276.48mhz -> DDR PLL2->PLLDIV4 = 0x8008; PLL2->PLLDIV5 = 0x8000; //GoCmd for PostDivider to take effect PLL2->PLLCMD = 0x00000001; UTIL_waitLoop(150); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL1_CONFIG) & 0x07000000) == 0x07000000)); UTIL_waitLoop(4100); //Enable the PLL2 PLL2->PLLCTL |= 0x00000001; // PLLEN=0 //do this after PLL's have been set up SYSTEM->PERI_CLKCTRL = 0x0BFF077C; return E_PASS; }Uint32 DEVICE_PLL2Init_173MHZ(){ unsigned int CLKSRC=0x0; /*Power up the PLL*/ PLL2->PLLCTL &= 0xFFFFFFFD; /*Select the Clock Mode as Onchip Oscilator or External Clock on MXI pin*/ /*VDB has input on MXI pin */ PLL2->PLLCTL &= 0xFFFFFEFF; PLL2->PLLCTL |= CLKSRC<<8; /*Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR*/ PLL2->PLLCTL &= 0xFFFFFFDF; /*Set PLLEN=0 => PLL BYPASS MODE*/ PLL2->PLLCTL &= 0xFFFFFFFE; UTIL_waitLoop(50); // PLLRST=1(reset assert) PLL2->PLLCTL |= 0x00000008; UTIL_waitLoop(300); /*Bring PLL out of Reset*/ PLL2->PLLCTL &= 0xFFFFFFF7; //Program the Multiper and Pre-Divider for PLL2 PLL2->PLLM = 0xE0; // VCO will 24*2M/N+1 = 344.064Mhz PLL2->PREDIV = 0x8000|0x18; PLL2->POSTDIV = 0x8000; PLL2->SECCTL = 0x00470000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 PLL2->SECCTL = 0x00460000; // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 PLL2->SECCTL = 0x00400000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 PLL2->SECCTL = 0x00410000; // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 // Post divider setting for PLL2 PLL2->PLLDIV2 = 0x8000; PLL2->PLLDIV3 = 0x8001; // POST DIV 344.064/2 -> DDR PLL2->PLLDIV4 = 0x8006; PLL2->PLLDIV5 = 0x8000; //GoCmd for PostDivider to take effect PLL2->PLLCMD = 0x00000001; UTIL_waitLoop(150); /*Wait for PLL to LOCK */ while(! (((SYSTEM->PLL1_CONFIG) & 0x07000000) == 0x07000000)); UTIL_waitLoop(4100); //Enable the PLL2 PLL2->PLLCTL |= 0x00000001; // PLLEN=0 //do this after PLL's have been set up SYSTEM->PERI_CLKCTRL = 0x0BFF05FC; return E_PASS; }// MJL replaced the DDR configuration with one that's (mostly) from the DVSDK4///* Uint32 DEVICE_DDR2Init(){ DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) & 0xFFFF9F3F; // Set bit CLRZ (bit 13) SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) | 0x00002000; // Check VTP READY Status while( !(SYSTEM->VTPIOCR & 0x8000)); // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000; // Set bit LOCK(bit7) and PWRSAVE (bit8) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00000080; // Powerdown VTP as it is locked (bit 6) // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004040; // Wait for calibration to complete UTIL_waitLoop( 150 ); // Set the DDR2 to synreset, then enable it again DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); DDR->DDRPHYCR = 0x000000C5; DDR->SDBCR = 0x08D34832; //Program SDRAM Bank Config Register DDR->SDBCR = 0x0853C832; DDR->SDTIMR =0x3C934B51; //Program SDRAM Timing Control Register1 DDR->SDTIMR2 =0x4221C72; //Program SDRAM Timing Control Register2 DDR->PBBPR = 0x000000FE; DDR->SDBCR = 0x08534832; //Program SDRAM Bank Config Register DDR->SDRCR = 0x00000768; //Program SDRAM Refresh Control Register DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); return E_PASS;} */// MJL ripped off the DDR timings and the setup functions from the TI bootloaderstatic const Uint16 DDR_T_RFC = 1275;static const Uint16 DDR_T_RP = 200;static const Uint16 DDR_T_RCD = 200;static const Uint16 DDR_T_WR = 150 ;static const Uint16 DDR_T_RAS = 450;static const Uint16 DDR_T_RC = 650;static const Uint16 DDR_T_RRD = 100;static const Uint16 DDR_T_WTR = 100;static const Uint32 DDR_T_RASMAX = 700000;static const Uint16 DDR_T_XP = 2;static const Uint16 DDR_T_XSNR = 1375;static const Uint16 DDR_T_XSRD = 199;static const Uint16 DDR_T_RTP = 75;static const Uint16 DDR_T_CKE = 3;static const Uint16 DDR_RR = 78;//#define DDR_FREQ (IS_DM368?340:243) // MJL added///*Uint32 DDR_Get_Val(Uint32 parm, Uint32 freq){ Uint32 result; result = ((parm * freq) / 10000) - 1; // Check if value calculated from formula results in decimal. // If yes round off to next decimal, as the value to be // written to register should be >= calculated value. // if((parm * freq) % 10000) result++; return result;}*/// MJL do inline, seems realtime divide operations aren't linked in???#define DDR_Get_Val(parm, freq) (((parm*freq)/10000)-1+(((parm*freq)%10000)!=0))// MJL revise the calculation to a more sensible one?//#define DDR_Get_Val(parm, freq) (((parm*freq)/10000))Uint32 DEVICE_DDR2Init(){ Uint32 tRFC, tRP, tRCD, tWR, tRAS, tRC, tRRD, tWTR; DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) & 0xFFFF9F3F; // Set bit CLRZ (bit 13) SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) | 0x00002000; // Check VTP READY Status while( !(SYSTEM->VTPIOCR & 0x8000)); // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000; // Set bit LOCK(bit7) and PWRSAVE (bit8) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00000080; // Powerdown VTP as it is locked (bit 6) // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004040; // Wait for calibration to complete UTIL_waitLoop( 150 ); // Set the DDR2 to synreset, then enable it again DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); DDR->DDRPHYCR = 0x000000C5; DDR->SDBCR = 0x534832; DDR->SDBCR = 0x53C832; // 0x53C832; Set the TIMUNLOCK to write into the TMR reg tRFC = DDR_Get_Val(DDR_T_RFC, DDR_FREQ); tRP = DDR_Get_Val(DDR_T_RP, DDR_FREQ); tRCD = DDR_Get_Val(DDR_T_RCD, DDR_FREQ); tWR = DDR_Get_Val(DDR_T_WR, DDR_FREQ); tRAS = DDR_Get_Val(DDR_T_RAS, DDR_FREQ); tRC = DDR_Get_Val(DDR_T_RC, DDR_FREQ); tRRD = DDR_Get_Val(DDR_T_RRD, DDR_FREQ); tWTR = DDR_Get_Val(DDR_T_WTR, DDR_FREQ); DDR->SDTIMR = tRFC << 25 | tRP << 22 | tRCD << 19 | tWR << 16 | tRAS << 11 | tRC << 6 | tRRD << 3 | tWTR << 0; DDR->SDTIMR2 = ((DDR_T_RASMAX / (DDR_RR * DDR_FREQ)) << 27) | (DDR_T_XP << 25 ) | (((DDR_T_XSNR * DDR_FREQ) / 10000) << 16) | (DDR_T_XSRD << 8) | (((DDR_T_RTP * DDR_FREQ) / 10000) << 5) | (DDR_T_CKE << 0); DDR->SDBCR = 0x534832; //0x534832; Reset the TIMUNLOCK TMR Write Disable DDR->PBBPR = 0x000000FE; DDR->SDBCR = 0xD34A32; //Enable DDR2 and DDR and SDram. Write '1' to BOOTUNLOCK DDR->SDBCR = 0x534A32; //Enable DDR2 and DDR and SDram. Write '0' to BOOTUNLOCK DDR->SDRCR = (DDR_RR * DDR_FREQ) / 10; //Program SDRAM Refresh Control Registers DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); return E_PASS;}Uint32 DEVICE_DDR2Init_270MHZ(){ DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) & 0xFFFF9F3F; // Set bit CLRZ (bit 13) SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) | 0x00002000; // Check VTP READY Status while( !(SYSTEM->VTPIOCR & 0x8000)); // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000; // Set bit LOCK(bit7) and PWRSAVE (bit8) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00000080; // Powerdown VTP as it is locked (bit 6) // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004040; // Wait for calibration to complete UTIL_waitLoop( 150 ); // Set the DDR2 to synreset, then enable it again DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); DDR->DDRPHYCR = 0x000000C6; DDR->SDBCR = 0x00D34A32; //Program SDRAM Bank Config Register DDR->SDBCR = 0x0053CA32; DDR->SDTIMR = 0x45245392; //Program SDRAM Timing Control Register1 DDR->SDTIMR2 = 0x4225C742; //Program SDRAM Timing Control Register2 DDR->PBBPR = 0x000000FE; DDR->SDBCR = 0x00534A32; //Program SDRAM Bank Config Register DDR->SDRCR = 0x0000083A; //Program SDRAM Refresh Control Register DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); return E_PASS;}Uint32 DEVICE_DDR2Init_216MHZ(){ DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) & 0xFFFF9F3F; // Set bit CLRZ (bit 13) SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) | 0x00002000; // Check VTP READY Status while( !(SYSTEM->VTPIOCR & 0x8000)); // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000; // Set bit LOCK(bit7) and PWRSAVE (bit8) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00000080; // Powerdown VTP as it is locked (bit 6) // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004040; // Wait for calibration to complete UTIL_waitLoop( 150 ); // Set the DDR2 to synreset, then enable it again DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); DDR->DDRPHYCR = 0x000000C5; DDR->SDBCR = 0x08D34832; //Program SDRAM Bank Config Register DDR->SDBCR = 0x0853C832; DDR->SDTIMR = 0x369342D1; //Program SDRAM Timing Control Register1 DDR->SDTIMR2 = 0x421DC702; //Program SDRAM Timing Control Register2 DDR->PBBPR = 0x000000FE; DDR->SDBCR = 0x08534832; //Program SDRAM Bank Config Register DDR->SDRCR = 0x00000695; //Program SDRAM Refresh Control Register DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); return E_PASS;}Uint32 DEVICE_DDR2Init_277MHZ(){ DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) & 0xFFFF9F3F; // Set bit CLRZ (bit 13) SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) | 0x00002000; // Check VTP READY Status while( !(SYSTEM->VTPIOCR & 0x8000)); // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000; // Set bit LOCK(bit7) and PWRSAVE (bit8) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00000080; // Powerdown VTP as it is locked (bit 6) // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004040; // Wait for calibration to complete UTIL_waitLoop( 150 ); // Set the DDR2 to synreset, then enable it again DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); DDR->DDRPHYCR = 0x000000C5; DDR->SDBCR = 0x08D34832; //Program SDRAM Bank Config Register DDR->SDBCR = 0x0853C832; DDR->SDTIMR = 0x4ADC5C1A; //Program SDRAM Timing Control Register1 DDR->SDTIMR2 = 0x4ADC5C1A; //Program SDRAM Timing Control Register2 DDR->PBBPR = 0x000000FE; DDR->SDBCR = 0x08534832; //Program SDRAM Bank Config Register DDR->SDRCR = 0x0000090D; //Program SDRAM Refresh Control Register DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); return E_PASS;}Uint32 DEVICE_DDR2Init_173MHZ(){ DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) & 0xFFFF9F3F; // Set bit CLRZ (bit 13) SYSTEM->VTPIOCR = (SYSTEM->VTPIOCR) | 0x00002000; // Check VTP READY Status while( !(SYSTEM->VTPIOCR & 0x8000)); // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) //SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004000; // Set bit LOCK(bit7) and PWRSAVE (bit8) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00000080; // Powerdown VTP as it is locked (bit 6) // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) SYSTEM->VTPIOCR = SYSTEM->VTPIOCR | 0x00004040; // Wait for calibration to complete UTIL_waitLoop( 150 ); // Set the DDR2 to synreset, then enable it again DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); DDR->DDRPHYCR = 0x000000C5; DDR->SDBCR = 0x08D34832; //Program SDRAM Bank Config Register DDR->SDBCR = 0x0853C832; DDR->SDTIMR = 0x2C923251; //Program SDRAM Timing Control Register1 DDR->SDTIMR2 = 0x4217C722; //Program SDRAM Timing Control Register2 DDR->PBBPR = 0x000000FE; DDR->SDBCR = 0x0853483; //Program SDRAM Bank Config Register DDR->SDRCR = 0x00000546; //Program SDRAM Refresh Control Register DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_DDR2,0,PSC_ENABLE); return E_PASS;}Uint32 DEVICE_EMIFInit(){#if 0 Uint32 currCE = 0; Uint32 width; VUint32 *ABCR = NULL; // Set width to 8 or 16 width = (DEVICE_emifBusWidth() == DEVICE_BUSWIDTH_8BIT)? 0 : 1; // Set PINMUX for EMIF use DEVICE_pinmuxControl(2,DEVICE_PINMUX_EMIF_MASK,DEVICE_PINMUX_EMIF_EN); // FIXME AEMIF->AWCCR &= ( ~(DEVICE_EMIF_AWCC_WAITSTATE_MASK) | 0xFF ); ABCR = &(AEMIF->AB1CR); while (currCE < DEVICE_EMIF_NUMBER_CE_REGION) { ABCR[currCE++] = 0x3FFFFFFC | width; // Adjust for quicker access times }#endif AEMIF->AWCCR = 0xff; AEMIF->A1CR = 0x40400204; AEMIF->NANDFCR |= 1; AEMIF->A2CR = 0x00a00505; return E_PASS; } Uint32 DEVICE_UART0Init(){ #if 0 Uint16 divider; // Reset and then power on the UART0 via PSC DEVICE_LPSCTransition(LPSC_UART0,PD0,PSC_SYNCRESET); DEVICE_LPSCTransition(LPSC_UART0,PD0,PSC_ENABLE); // Put UART in reset UART0->PWREMU_MGNT = 0; UTIL_waitLoop(10000); // Set free running UART0->PWREMU_MGNT = 0x0001; // Set DLAB bit - allows setting of clock divisors UART0->LCR |= 0x80; UTIL_waitLoop(100); //divider = 24000000/(16*115200) = 13.02 => 13 = 0x0D => 24000000/(16*13) = 115384 (0.16% error) //divider = DEVICE_OSC_FREQ / (DEVICE_UART0_DESIRED_BAUD * DEVICE_UART0_OVERSAMPLE_CNT); //dividerX2 = (2*DEVICE_OSC_FREQ) / (DEVICE_UART0_DESIRED_BAUD * DEVICE_UART0_OVERSAMPLE_CNT); //if (divider*2 < dividerX2) divider++; divider = 0x0D; UART0->DLL = divider & 0xFF; UART0->DLH = (divider >> 8) & 0xFF; // Enable, clear and reset FIFOs UART0->FCR = 0x0; UTIL_waitLoop(100); UART0->FCR = 0xC1; UTIL_waitLoop(100); // Disable autoflow control UART0->MCR = 0x00; UTIL_waitLoop(100); // Set word length to 8 bits, no parity, one stop bit, clear DLAB bit UART0->LCR = 0x03; UTIL_waitLoop(100); // Enable interrupts UART0->IER = 0x07; UTIL_waitLoop(100); // Set to run free UART0->PWREMU_MGNT |= 0x6001; UTIL_waitLoop(100); if ( (UART0->IIR & 0xC0) != 0xC0 ) return E_FAIL; UTIL_waitLoop(100); // Disable the timer TIMER0->TCR = 0x00000000; // Set to 64-bit GP Timer mode, enable TIMER12 & TIMER34 TIMER0->TGCR = 0x00000003; // Reset timers to zero TIMER0->TIM34 = 0x00000000; TIMER0->TIM12 = 0x00000000; // Set timer period (5 second timeout = (24000000 * 5) cycles = 0x080BEFC0) TIMER0->PRD34 = 0x00000000; TIMER0->PRD12 = 0x07270E00;#endif UART0->PWREMU_MGNT = 0; // Reset UART TX & RX components UTIL_waitLoop( 100 ); UART0->MDR = 0x0; UART0->DLL = 0xd; // Set baud rate UART0->DLH = 0; UART0->FCR = 0x0007; // Clear UART TX & RX FIFOs UART0->FCR = 0x0000; // Non-FIFO mode UART0->IER = 0x0007; // Enable interrupts UART0->LCR = 0x0003; // 8-bit words, // 1 STOP bit generated, // No Parity, No Stick paritiy, // No Break control UART0->MCR = 0x0000; // RTS & CTS disabled, // Loopback mode disabled, // Autoflow disabled UART0->PWREMU_MGNT = 0xE001; // Enable TX & RX componenets return E_PASS;}Uint32 DEVICE_I2C0Init(){ #if 0 Uint32 iCLK = 0; Uint32 iPSC = 2; Uint32 D = 5; // Enable the Xmt, Master Mode, free running, 7-bit address, 8-bit words, no DLB I2C0->ICMDR = I2C_ICMDR_MST | // Set MST - Master mode I2C_ICMDR_TRX | // Set TRX - Transmitter I2C_ICMDR_FRE; UTIL_waitLoop(1000); // Set the DM648 address I2C0->ICOAR = DEVICE_I2C_OWN_ADDRESS & 0xFF; // Set Default I2C High and Low Clock Hold // Set prescalar to 2 (Scaled clock = input clk / PSC+1) // Input clock is 24MHz // Scaled clock will be 8MHz I2C0->ICPSC = (Uint32)(0xFF & iPSC); //iCLK = (24000000)/((2+1)*DEVICE_I2C_TARGET_FREQ*2) - D; iCLK = 20-D; I2C0->ICCLKH = (Uint32)(0xFF & iCLK); I2C0->ICCLKL = (Uint32)(0xFF & iCLK); // Enable the Xmt, Master Mode, free running, 7-bit address, 8-bit words, no DLB I2C0->ICMDR = I2C_ICMDR_MST | // Set MST - Master mode I2C_ICMDR_TRX | // Set TRX - Transmitter I2C_ICMDR_FRE; // Set backward compatibility mode I2C0->ICEMDR = I2C_ICEMDR_EXTMODE; I2C0->ICIMR = 0; // Read and clear interrupt status register I2C0->ICSTR |= 0x0000703F; // Read ICIVR until clear while ((I2C0->ICIVR & 0x7) != 0x0); // Take I2C Out of Reset I2C0->ICMDR = I2C_ICMDR_MST | // Set MST - Master mode I2C_ICMDR_TRX | // Set TRX - Transmitter I2C_ICMDR_FRE | // Set free running I2C_ICMDR_IRS; UTIL_waitLoop(1000);#endif I2C0->ICMDR = 0; // Reset I2C I2C0->ICPSC = 26; // Config prescaler for 27MHz I2C0->ICCLKL = 20; // Config clk LOW for 20kHz I2C0->ICCLKH = 20; // Config clk HIGH for 20kHz I2C0->ICMDR |= I2C_ICMDR_IRS; // Release I2C from reset return E_PASS;}Uint32 DEVICE_I2C0Reset(){ I2C0->ICMDR &= ~I2C_ICMDR_IRS; UTIL_waitLoop(200); // Read and clear interrupt status register I2C0->ICSTR |= 0x00007FFF; // Read ICIVR until clear while ((I2C0->ICIVR & 0x7) != 0x0); // Take I2C Out of Reset I2C0->ICMDR |= I2C_ICMDR_IRS; UTIL_waitLoop(200); return E_PASS;}Uint32 DEVICE_TIMER0Init(){ // Put timer into reset TIMER0->EMUMGT_CLKSPD = 0x00000003; TIMER0->TCR = 0x00000000; // Enable TINT0, TINT1 interrupt TIMER0->INTCTL_STAT = 0x00000001; // // Set to 64-bit GP Timer mode, enable TIMER12 & TIMER34 TIMER0->TGCR = 0x00000003; // Reset timers to zero TIMER0->TIM12 = 0x00000000; TIMER0->TIM34 = 0x00000000; // Set timer period (5 second timeout = (24000000 * 5) cycles = 0x07270E00) TIMER0->PRD34 = 0x00000000; TIMER0->PRD12 = 0x07270E00; return E_PASS;}//interrupt for Timer0 in DM35x and DM36x is the samevoid DEVICE_TIMER0Start(void){ // Clear interrupt AINTC->IRQ1 |= 0x00000001; // Put timer in reset TIMER0->TGCR = 0x00000000; // Reset timer count to zero TIMER0->TIM12 = 0x00000000; // Setup for one-shot mode TIMER0->TCR = 0x00000040; // Start TIMER12 TIMER0->TGCR = 0x00000005;}void DEVICE_TIMER0Stop(void){ // Clear interrupt AINTC->IRQ1 |= 0x00000001; // Put timer in reset TIMER0->TCR = 0x00000000; TIMER0->TGCR = 0x00000000; // Reset timer count to zero TIMER0->TIM12 = 0x00000000;}Uint32 DEVICE_TIMER0Status(void){ return ((AINTC->IRQ1)&0x1);}/************************************************************* Local Function Definitions *************************************************************//************************************************************ End file ************************************************************/
Hi Pablo,
Thank you for your fast response.
Because of the time reasons, i sincerely want to wait. ......
But we want to know the performance of leopardboard dm368 work in 432MHz can be achieved video 1080p encode 30 frames at least.
so , are there easier way to achieve, or you can inform the relevant file name ?
thanks for your help, again.
Eric Pan
Thank you for your help and guide me a good direction,
I will continue to study and try these information.
Many thanks for your help
Best Regards,
Also is the "High Definition 720p USB Webcam" binary code from Leopard Imaging working on the Leopard Board DM368?
Yes, it works on the Leopardboard 368.
gentlemich Also is the "High Definition 720p USB Webcam" binary code from Leopard Imaging working on the Leopard Board DM368?
Hi Mark Lesha,
I had built the ubl, seems it work ok,
but when i run the demo from dvsdk,
decode -v xxx.264 -y3 or decode -v xxx.264 -y5 ,
It no video ouput, and encode only 11fps .
Could you tell me where i need to modify ? is u-boot or kernel ?
my environment as following
dvsdk_4_02_00_06
psp03.01.01.39
Leopard DM368
------------------------------------------------------------------------------
following is my test result:
root@dm368-evm:/usr/share/ti/dvsdk-demos# cat /proc/davinci_clocks
ref_clk users=18 24000000 Hz
pll1 users=16 pll 702000000 Hz
pll1_aux_clk users= 5 pll 24000000 Hz
uart0 users= 1 psc 24000000 Hz
i2c users= 1 psc 24000000 Hz
spi4 users= 0 psc 24000000 Hz
pwm0 users= 0 psc 24000000 Hz
pwm1 users= 0 psc 24000000 Hz
pwm2 users= 0 psc 24000000 Hz
timer0 users= 1 psc 24000000 Hz
timer1 users= 0 psc 24000000 Hz
timer2 users= 2 psc 24000000 Hz
timer3 users= 0 psc 24000000 Hz
usb users= 1 psc 24000000 Hz
pll1_sysclkbp users= 0 pll 24000000 Hz
clkout0 users= 0 pll 24000000 Hz
pll1_sysclk1 users= 0 pll 702000000 Hz
pll1_sysclk2 users= 0 pll 351000000 Hz
pll1_sysclk3 users= 2 pll 351000000 Hz
vpss_dac users= 1 psc 351000000 Hz
mjcp users= 1 psc 351000000 Hz
pll1_sysclk4 users= 7 pll 175500000 Hz
uart1 users= 1 psc 175500000 Hz
mmcsd1 users= 0 psc 175500000 Hz
spi0 users= 1 psc 175500000 Hz
spi1 users= 0 psc 175500000 Hz
spi2 users= 0 psc 175500000 Hz
spi3 users= 0 psc 175500000 Hz
gpio users= 1 psc 175500000 Hz
aemif users= 2 psc 175500000 Hz
emac users= 1 psc 175500000 Hz
asp0 users= 1 psc 175500000 Hz
rto users= 0 psc 175500000 Hz
pll1_sysclk5 users= 1 pll 351000000 Hz
vpss_master users= 1 psc 351000000 Hz
pll1_sysclk6 users= 0 pll 27000000 Hz
pll1_sysclk7 users= 0 pll 702000000 Hz
pll1_sysclk8 users= 1 pll 100285714 Hz
mmcsd0 users= 1 psc 100285714 Hz
pll1_sysclk9 users= 0 pll 351000000 Hz
pll2 users= 2 pll 445440000 Hz
pll2_aux_clk users= 0 pll 24000000 Hz
clkout1 users= 1 pll 24000000 Hz
pll2_sysclk1 users= 0 pll 445440000 Hz
pll2_sysclk2 users= 1 pll 445440000 Hz
arm_clk users= 1 psc 445440000 Hz
pll2_sysclk3 users= 0 pll 445440000 Hz
pll2_sysclk4 users= 0 pll 20247272 Hz
voice_codec users= 0 psc 20247272 Hz
pll2_sysclk5 users= 0 pll 74240000 Hz
pll2_sysclk6 users= 0 pll 445440000 Hz
pll2_sysclk7 users= 0 pll 445440000 Hz
pll2_sysclk8 users= 0 pll 445440000 Hz
pll2_sysclk9 users= 0 pll 445440000 Hz
pwm3 users= 0 psc 24000000 Hz
root@dm368-evm:/usr/share/ti/dvsdk-demos#
Bytes transferred = 2157552 (20ebf0 hex)
## Booting kernel from Legacy Image at 80700000 ...
Image Name: Linux-2.6.32.17-davinci1-g044c34
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2157488 Bytes = 2.1 MB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
Uncompressing Linux............................................................................................................................................. done, booting the kernel.
Linux version 2.6.32.17-davinci1-g044c347-dirty (ubuntu@ubuntu-desktop) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) ) #22 PREEMPT Thu Jun 23 05:48:19 MDT 2011
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: DaVinci DM36x EVM
Memory policy: ECC disabled, Data cache writeback
DaVinci dm36x_rev1.2 variant 0x8
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 12192
Kernel command line: console=ttyS0,115200n8 noinitrd rw ip=dhcp root=/dev/nfs nfsroot=192.168.0.12:/home/ubuntu/dm368/dvsdk_4_02/filesysdec,nolock mem=48M video=davincifb:vid0=OFF:vid1=OFF dm365_imp.oper_mode=0 davinci_capture.device_type=4 vpfe_capture.cont_bufsize=37748736
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 48MB = 48MB total
Memory: 44076KB available (4044K code, 393K data, 144K init, 0K highmem)
SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:245
Console: colour dummy device 80x30
Calibrating delay loop... 222.00 BogoMIPS (lpj=1110016)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
DaVinci: 8 gpio irqs
NET: Registered protocol family 16
MUX: initialized INT_EDMA_CC
MUX: Setting register INT_EDMA_CC
INTMUX (0x00000018) = 0x00000000 -> 0x00000004
davinci_serial_init:97: failed to get UART2 clock
MUX: initialized INT_EMAC_RXTHRESH
MUX: Setting register INT_EMAC_RXTHRESH
INTMUX (0x00000018) = 0x00000004 -> 0x00004004
MUX: initialized INT_EMAC_RXPULSE
MUX: Setting register INT_EMAC_RXPULSE
INTMUX (0x00000018) = 0x00004004 -> 0x0000c004
MUX: initialized INT_EMAC_TXPULSE
MUX: Setting register INT_EMAC_TXPULSE
INTMUX (0x00000018) = 0x0000c004 -> 0x0001c004
MUX: initialized INT_EMAC_MISCPULSE
MUX: Setting register INT_EMAC_MISCPULSE
INTMUX (0x00000018) = 0x0001c004 -> 0x0003c004
MUX: initialized GPIO33
MUX: Setting register GPIO33
PINMUX4 (0x00000010) = 0x55715455 -> 0x55714455
MUX: initialized GPIO40
MUX: Setting register GPIO40
PINMUX4 (0x00000010) = 0x55714455 -> 0x51714455
EVM: HD imager video input
MUX: initialized INT_PRTCSS
MUX: Setting register INT_PRTCSS
INTMUX (0x00000018) = 0x0003c004 -> 0x0003c404
MUX: initialized SPI0_SCLK
MUX: Setting register SPI0_SCLK
PINMUX3 (0x0000000c) = 0x015affff -> 0x115affff
MUX: initialized SPI0_SDI
MUX: Setting register SPI0_SDI
PINMUX3 (0x0000000c) = 0x115affff -> 0x155affff
MUX: initialized SPI0_SDO
MUX: Setting register SPI0_SDO
PINMUX3 (0x0000000c) = 0x155affff -> 0x175affff
MUX: initialized SPI0_SDENA0
MUX: Setting register SPI0_SDENA0
PINMUX3 (0x0000000c) = 0x175affff -> 0x375affff
Leopard : dm365leopard_tlv320aic3x_configure
Leopard: DM365 Leopard tlv320aic3x configure
MUX: initialized CLKOUT1
MUX: Setting register CLKOUT1
PINMUX4 (0x00000010) = 0x51714455 -> 0x51734455
Leopard : dm365leopard_tlv320aic3x_configure end
Leopard: DM365 Leopard tlv320aic3x configure end
Leopard : dm365_evm_init
bio: create slab <bio-0> at 0
DM365 IPIPE initialized in Continuous mode
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pca9543a_probe
vpss vpss: dm365_vpss vpss probed
vpss vpss: dm365_vpss vpss probe success
dm365_afew_hw_init
ch0 default output "COMPOSITE", mode "NTSC"
VPBE Encoder Initialized
cfg80211: Using static regulatory domain info
cfg80211: Regulatory domain: US
(start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
(2402000 KHz - 2472000 KHz @ 40000 KHz), (600 mBi, 2700 mBm)
(5170000 KHz - 5190000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5190000 KHz - 5210000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5210000 KHz - 5230000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5230000 KHz - 5330000 KHz @ 40000 KHz), (600 mBi, 2300 mBm)
(5735000 KHz - 5835000 KHz @ 40000 KHz), (600 mBi, 3000 mBm)
cfg80211: Calling CRDA for country: US
LogicPD encoder initialized
Switching to clocksource timer0_1
musb_hdrc: version 6.0, cppi-dma, hoNAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron NAND 256MiB 3,3V 8-bit)
2 NAND chips detected
Bad block table not found for chip 0
Bad block table not found for chip 1
Scanning device for bad blocks
Creating 5 MTD partitions on "davinci_nand.0":
0x000000000000-0x0000003c0000 : "bootloader"
0x0000003c0000-0x000000400000 : "params"
0x000000400000-0x000000c00000 : "kernel"
0x000000c00000-0x000008c00000 : "filesystem1"
0x000008c00000-0x000020000000 : "filesystem2"
davinci_nand davinci_nand.0: controller rev. 2.3
spi_davinci spi_davinci.0: DaVinci SPI driver in EDMA mode
Using RX channel = 17 , TX channel = 16 and event queue = 3
at25 spi0.0: 8 KByte at25640 eeprom, pagesize 32
spi_davinci spi_davinci.0: Controller at 0xfec66000
console [netcon0] enabled
netconsole: network logging started
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver usbtest
mice: PS/2 mouse device common for all mice
tsc2004: probe of 1-0049 failed with error -121
i2c /dev entries driver
Linux video capture interface: v2.00
ths7303 1-002c: chip found @ 0x58 (DaVinci I2C adapter)
vpfe_init
vpfe-capture: vpss clock vpss_master enabled
vpfe-capture vpfe-capture: v4l2 device registered
vpfe-capture vpfe-capture: video device registered
EVM: switch to tvp5146 SD video input
tvp514x 1-005d: tvp514x 1-005d decoder driver registered !!
vpfe-capture vpfe-capture: v4l2 sub device tvp5146 registered
EVM: switch to tvp7002 HD video input
........ (i didn't plug the video card , ^^")
vpfe-capture vpfe-capture: v4l2 sub device tvp7002 register fails
ths7353 1-002e: chip found @ 0x5c (DaVinci I2C adapter)
ths7353 1-002e: No platform data!!
ths7353 1-002e: ths7353 write failed
ths7353: probe of 1-002e failed with error -121
vpfe-capture vpfe-capture: v4l2 sub device ths7353 register fails
vpfe_register_ccdc_device: DM365 ISIF
DM365 ISIF is registered with vpfe.
af major#: 252, minor# 0
AF Driver initialized
aew major#: 251, minor# 0
AEW Driver initialized
Trying to register davinci display video device.
layer=c1155800,layer->video_dev=c1155970
layer=c1155c00,layer->video_dev=c1155d70
davinci_init:DaVinci V4L2 Display Driver V1.0 loaded
watchdog watchdog: heartbeat 60 sec
davinci_mmc davinci_mmc.0: Using DMA, 4-bit mode
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
Advanced Linux Sound Architecture Driver Version 1.0.21.
No device for DAI tlv320aic3x
No device for DAI davinci-i2s
asoc: tlv320aic3x <-> davinci-i2s mapping ok
ALSA device list:
#0: DaVinci EVM (tlv320aic3x)
TCP cubic registered
NET: Registered protocol family 17
lib80211: common routines for IEEE802.11 drivers
Clocks: disable unused mmcsd1
Clocks: disable unused spi1
Clocks: disable unused spi2
Clocks: disable unused spi3
Clocks: disable unused spi4
Clocks: disable unused pwm0
Clocks: disable unused pwm1
Clocks: disable unused pwm2
Clocks: disable unused pwm3
Clocks: disable unused timer1
Clocks: disable unused timer3
Clocks: disable unused emac
Clocks: disable unused voice_codec
Clocks: disable unused rto
Clocks: disable unused mjcp
davinci_emac_probe: using random MAC addr: d2:93:87:a3:82:6c
emac-mii: probed
mmc0: new high speed SD card at address b368
mmcblk0: mmc0:b368 SDC 1.85 GiB
mmcblk0: p1 p2
eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=1:01, id=221613)
Sending DHCP requests .
PHY: 1:01 - Link is Up - 100/Full
., OK
IP-Config: Got DHCP answer from 0.0.0.0, my address is 192.168.0.53
IP-Config: Complete:
device=eth0, addr=192.168.0.53, mask=255.255.255.0, gw=192.168.0.1,
host=192.168.0.53, domain=kbronet.com.tw, nis-domain=(none),
bootserver=0.0.0.0, rootserver=192.168.0.12, rootpath=
Looking up port of RPC 100003/2 on 192.168.0.12
Looking up port of RPC 100005/1 on 192.168.0.12
VFS: Mounted root (nfs filesystem) on device 0:14.
Freeing init memory: 144K
INIT: version 2.86 booting
Please wait: booting...
Starting udev
FAT: bogus number of reserved sectors
VFS: Can't find a valid FAT filesystem on dev mmcblk0.
VFS: Can't find a valid FAT filesystem on dev mmcblk0p2.
Remounting root file system...
Caching udev devnodes
Populating dev cachemv: cannot rename '/tmp/devices': No such file or directory
ALSA: Restoring mixer settings...
NOT configuring network interfaces: / is an NFS mount
hwclock: can't open '/dev/misc/rtc': No such file or directory
Thu Mar 24 19:02:00 UTC 2011
INIT: Entering runlevel: 5
Starting system message bus: dbus.
Starting telnet daemon.
modprobe: FATAL: Could not open 'kernel/net/ipv6/ipv6.ko': No such file or directory
Starting syslogd/klogd: done
Starting thttpd.
We're not currently using the DVSDK4.02, only the RidgeRun free SDK.
DVSDK4.02 is for the TI DVEVM hardware and not Leopardboard, so you might have to do some things to it to get it to work on Leopardboard. For example, lack of video output could be due to video not set up in the kernel bootargs, or perhaps because of missing initialization of the THS7303 video output buffer (component video). Re the THS7303, the DVEVM apparently has a THS7303 but it is on the component video input, not the output. I think we removed that THS7303 initialization from the BSP file and did our own THS7303 handling within our applications, just by using the I2C interface.
The devices.c code I gave above does have PLL settings that produce valid SD and HD video, on both composite and component outputs. If the ratios are incorrect your monitor may say something like 'unsupported format'.
I think the 'decode' demo of DVSDK could work, but you might have trouble with 'encode'. Last time I used the DVSDK, I had to modify DMAI to get video from the CCDC sensor, since it only supported component video input as provided by the TI DVEVM.
Hi, Mark Lesha,
Yes, I had modify some changes on demos of DVSDK4.02 and kernel.
The leopardBoard DM368 is work fine on component Input and output , Audio Input and output.
When i doing the 'encode 1080I' or 'decode 1080I' demo of DVSDK and Leopardboard DM368 work at 300MHz, it could be work fine. The performances that both 'decode' and 'encode' demos of DVSDK can be reach 23 fps .
I just change the ubl that above you provide.
The demo of DVSDK can't work again. I want to find out what happened.
If the PLL's sets are correct, and valid SD and HD video.
Can you tell me how to valid HD video?
Do u use the video codecs(h264enc,h264dec..etc) of TI to test SD/HD video?
thank for your help.
Best regards,
EricPan
Hi EricPan,
Yes we run the H264 and JPEG encoders via DMAI and we have CCDC camera capture and framebuffer video output in SD / HD resolutions on both composite and component, all working fine on both DM365 and DM368. So it's a bit strange. I checked your /proc/davinci_clocks list and it matches mine exactly. I did not use the video decoders or audio codecs recently, but I think if the H264 encode works there's no problem. I do notice a problem with the DVI daughterboard which I need to investigate, it stopped working when I changed the PLL's. But everything else seems good.
I noticed in your kernel boot listing, there is 'vid0=OFF:vid1=OFF'. Which means you won't have any video. I suspect that when the bootloader was updated, the kernel bootargs were lost. When you run with the DM365 and it is working, can you check the bootargs, and save them? I think you will find they are different. Maybe you can put them back manually (in bootloader use setenv bootargs, saveenv).
Our bootargs has the following to set the initial video mode and support video output up to 1080i, setup capture interface etc:
davinci_enc_mngr.ch0_output=COMPONENT davinci_enc_mngr.ch0_mode=720P-60 davinci_display.cont2_bufsize=6291456 vpfe_capture.cont_bufoffset=6291456 vpfe_capture.cont_bufsize=6291456 video=davincifb:vid0=1920*1080*16,16K:vid1=1920*1080*16,4050K:osd0=1920*1080*16,4050K:osd1=1920*1080*4,1215K dm365_imp.oper_mode=0 davinci_capture.device_type=4 vpfe_capture.interface=1
Sorry slowly reply and thank for your help.
My problem has been solved.
The problem is because SYS_VPSS_CLKCTL did not correctly set when initializing VENC.
In this version that the HDVICP to run at 74.24MHz, which is close enough to the rated 74.25MHz..
But the kernel source code restrictions to be 74.25MHz . After i changed the code , it work fine at 74.24MHz..
__raw_writel(0x38, IO_ADDRESS(SYS_VPSS_CLKCTL));
hi, EricPan,
I am trying to get the HD component input board to work without much sucess. Could you please share some experience? Thanks! Happy Holidays.